1. Field of the Invention
Example embodiments of the present disclosure relate to semiconductor packages and methods of fabricating the same and, more particularly, to chip carriers, semiconductor devices including the same, semiconductor packages including the same, and methods of fabricating the same.
2. Description of the Related Art
Recently, multi-chip stacked packages have become desirable in the electronics industry because high performance electric or electronic products with lighter, smaller and faster sophisticated electronic components are needed for sophisticated electronic systems. Accordingly, various technologies for stacking a plurality of semiconductor chips have been developed. The multi-chip stacked packages may allow the electric or electronic products to have a relatively larger memory capacity. Further, the multi-chip stacked packages may improve a packaging density or a packaging efficiency in a limited area.
Through silicon vias (TSVs) have been widely used as electrical connectors between the stacked chips. TSVs may penetrate the chips and may act as electrodes. Thus, when the TSVs are formed to act as the electrodes or the electrical connectors in the package processes, conventional bonding wires may not be required. Hence, when the TSVs are employed in the packages, various advantages can be obtained.
In addition to the multi-chip stack technologies and the TSV technologies, system-in-package technologies have been widely used in the package processes. According to the system-in-packages, two or more different kinds of chips may be mounted on a single substrate. According to an example of the system-in-packages, a logic chip may be mounted on a substrate and a memory chip may be stacked on a side of the logic chip that is opposite to the substrate. If different kinds of chips are vertically stacked on a substrate as described above, interposers may be disposed between the stacked chips as well as between a lowermost chip and the substrate to adjust contact pitches of the stacked chips. For example, a logic chip, an interposer and a memory chip may be sequentially stacked on the substrate.
When a planar area of the logic chip is greater than that of the memory chip, a thermal conductive media should be disposed around the memory chip to transfer heat from the logic chip toward an outside region, or the size of the stacked memory chip should be increased to have a similar size to that of the logic chip in order to provide a thermal conductive path. In addition, it may be necessary to cover the logic chip and the memory chip with a metallic heat spreader to increase the heat emission efficiency. However, if the metallic heat spreader is employed, the metallic heat spreader may cause a physical stress applied to the semiconductor chips (e.g., the logic chip and the memory chip). Further, an empty space may be provided between the stacked memory chip and the metallic heat spreader. The empty space may have a relatively poor thermal conductivity, thereby degrading the reliability of the system-in-packages.